1. Field of the Invention
The present invention generally relates to III-V semiconductor Field Effect Transistor (FET) manufacture and more particularly to improving yield and reliability in III-V semiconductor chip manufacture.
2. Background Description
An ideal Field Effect Transistor (FET) can be modeled simply as a current source (Isat) and a switch. A FET inverter may be modeled simply as a pair of the switches and current sources driving a load modeled as a capacitor (Cload). This model is valid as long as path resistance and/or device resistance is negligible. Under those conditions, and ignoring any propagation delays, circuit performance is determined by drive current (Isat) and load (Cload), i.e., Isat=CloaddV/dt. Wiring path resistance and internal device resistances, however, complicate the model and erode performance.
Path and device resistance introduce series resistance into the path. Normal device resistance is either channel resistance or source/drain resistance. Source/drain resistance may be attributed to diffusion resistance, which is the resistance in the source/drain diffusion between the channel and the capacitive load; and contact resistance, i.e., at the typically metal to diffusion connection between the source/drain diffusion and the capacitive load. While the source/drain diffusion may be shortened to reduce diffusion resistance, for example, by locating the load adjacent to the channel (e.g., forming contacts at the gate edges), contact resistance, arguably considered as path resistance, is still present. Because a bare metal to semiconductor contact forms a Schottkey diode, semiconductor manufacturing typically includes steps to form a resistive contact and, simultaneously, minimize contact resistance.
III-V semiconductor (e.g., GaAs, InP, InGaAs and etc.) manufacturing, for example, typically involves alloying metal with the doped semiconductor to form low-resistance contact. Unfortunately, however, absent using difficult process controls that require delicate and precise alloying steps, the contact alloy may penetrate too deeply beyond the diffusion and into underlying the substrate during contact formation, which can cause device shorts, e.g., source/drain to substrate shorts and/or source to drain shorts. These defects in a single transistor can ruin an entire IC chip.
FIG. 1 shows an example of a prior art III-V semiconductor device 50. The device is formed on a semiconductor wafer 52, a Gallium Arsenide (GaAs) wafer in this example. The GaAs wafer 52 includes a body doped substrate 54 (e.g., doped with an N-type dopant) supporting a heavily doped layer 56 (doped in this example with a P-type dopant) and a channel doped surface layer 58 (in this example body with a P-type dopant). Gate oxide 60 and gates 62 on surface layer 58 define the FETs with contacts 64 formed alloying metal with the semiconductor at device (N-type) source/drains at either end of the channels, i.e., either side of gates 62.
As is apparent in this example, the metal contacts 64 formed through the surface layer 58 into the heavily doped layer 56, essentially shorting the contacts to substrate and together. These shorts from deep alloy penetration in the contact area, cause heavy leakage in and to the doped substrate region. This heavy leakage is a very significant current loss for short channel devices and, if large enough may make defective (dis or non-functional) any the circuit that includes one or more of the devices.
The state of the art approach requires precisely controlling process time and temperature to control the alloy depth. Unfortunately, while the controlling ambient temperature within a chamber and for a specified period of time may be relatively easy, localized variations within the chamber at contact level, for example, may make it difficult to control the depth and contact profile with uniformity. Consequently, contact profile may vary from contact to contact, wafer site to site, and wafer to wafer. Further, post contact-formation, channel and re-growth materials used may degrade well-formed contacts to increase contact resistance and/or form mis-contacts.
Thus, there exists a need for improved contact formation in III-V semiconductor manufacturing, and more particularly for simplifying low resistance III-V semiconductor contact formation while avoiding contact to substrate and/or channel shorts to improve chip yield and reliability.